One known application of electronic power switches is in forming bridge circuits for the actuation of motors. These circuits include pairs of electronic switches connected in series between the poles of a high voltage power supply. The load, in this case a winding of the motor, is connected between the connection points of the pairs of switches. The switches of each pair are controlled in such a way that at any instant at most one of the two is closed. That is to say that both switches of a pair cannot be simultaneously closed.
The electronic switches are controlled by low voltage logic circuits which produce control signals at two levels relative to a reference voltage which, normally, is also the earth terminal of the circuit arrangement. For controlling the switches of the bridge connected to the positive pole of the power supply, the level of the logic circuit signals is shifted by means of suitable level shifter circuits.
A typical structure of a control circuit with a level shifter is schematically represented in FIG. 1. Four power transistors, for example, field effect transistors (FET) of n channel DMOS type, indicated as T1, T2, T3 and T4 are connected in series in pairs between the terminals, indicated with the earth symbol and V.sub.H, of a relatively high voltage DC power supply, for example 300 volts. A load L, for example a winding of a motor, is connected between the connection nodes of the switches of the two pairs. A control logic circuit, indicated as LG, produces control signals at two voltage levels, for example the ground level, or zero, and a relatively low supply voltage level V.sub.LL, typically five volts. These signals, available on the outputs of supply voltage level V.sub.LL, typically five volts. These signals, available on the outputs of the logic circuit LG are applied to the control terminals, that is to say the gate electrodes both of the "lower" transistors T2, T4 through respective driving circuits, and the "upper" transistors T1, T3, through respective level shifting and driving circuits, to switch the transistors on or off (conduction or cut-off) according to the sequence determined by the logic circuit LG. For simplicity of the drawing, only the driving circuits DR1 and DR2 for the transistors T1 and T2 and only the level shifter LS1 relating to the transistor T1 are shown; it is understood that similar circuits are provided for control of the transistors T3 and T4.
The driving circuit (DR2) of the transistor T2 is supplied with a relatively low voltage V.sub.L, for example 12 volts, sufficient to raise the gate electrode of T2 to a voltage, with respect to its source terminal (which is connected to ground) greater than the conduction threshold. The driving circuit DR1 of the transistor T1 is supplied with a voltage V.sub.c the value of which is substantially equal to V.sub.L provided by a "buffer" capacitor C connected between the connection node S1 (between the two transistors T1 and T2) and a charging circuit, not shown, the function of which is to maintain the capacitor C charged to the voltage V.sub.c.
The level shifter LS1 includes two substantially identical circuit branches each constituted by an n channel MOS transistor M1, M2 the source terminal of which is connected to the ground terminal and the drain terminal of which is connected to the supply terminal V.sub.c via the parallel connection of a resistor R1, R2 and a zener diode D1, D2. The gate terminals of the transistors M1 and M2 are connected to an output of the logic circuit LG, one directly and the other through an inverter INV1, such that the control signals which arrive at the two transistors are always complementary to one another.
The level shifter LS1 also includes a bistable (flip-flop) circuit, indicated as RS, supplied with the voltage V.sub.c, and having "set" and "reset" terminals S, R respectively, connected via respective inverters INV2 and INV3 to the drain electrodes, respectively, of transistors M1 and M2, and an output terminal Q connected to the input of the driving circuit DR1 of transistor T1. The logic operations of the R-S flip-flop are set forth in the following truth table.
______________________________________ Rn Sn Qn + 1 ______________________________________ 0 0 Qn 0 1 1 1 0 0 3 1 1 Indeterminate ______________________________________
In operation, the two transistors M1 and M2 are alternately brought to a conduction state by signals generated by the logic circuit LG. The current pulses which form in succession in the two resistors R1 and R2 produce the "set" and "reset" signals at the inputs S and R of the flip-flop RS. Consequently, the voltage level of the output signal Q from the flip-flop, relative to the voltage level of the node S1 (which varies substantially between 0 and V.sub.H based on the state of conduction of the transistors of the bridge), causes the driving circuit DR1 to apply a voltage signal between the gate and source electrodes of the transistor T1, a voltage signal which switches on or off the transistor T1.
The circuit described above can be improved, in a manner which will be illustrated hereinbelow, to ensure that during switching of the node S1 between 0 and V.sub.H, both the inputs of the flip-flop are at low level. However, both the circuit of FIG. 1 and the thus-improved circuit are subject, when formed as part of a monolithic integrated circuit, to possible spurious switching such that they cannot be utilized when it is essential to achieve absolute security in operation of the transistor bridge.
Spurious switching is due to the structure capacitances associated with the transistors M1 and M2. These capacitances, generally indicated as C1 and C2 in FIG. 1, are the sum of the capacitances between drain and source and between drain and substrate. In certain conditions, as will be explained in more detail hereinbelow in relation to a particular circuit, during discharge of these capacitances, which takes place in part through the Zener diodes, D1 and D2 and in part through the resistors R1 and R2, the conduction of parasitic components is triggered due to the structure of the integrated circuit in which the various components of the switching control circuit are formed, which can lead to switching signals at the flip-flop which are not those caused by the control signal and which can therefore cause very serious malfunctions.
The object of the present invention is to provide a switching control circuit with a level shifter for an electronic power switch in which spurious switching is not possible in any case.